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Results 1 to 25 of 834

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Raw pointers in application classes of C++ considered HarmfulSMIRNOV, Igor B.ACM SIGPLAN notices. 2007, Vol 42, Num 4, pp 23-30, issn 1523-2867, 8 p.Article

Increasing of the quality of energy from stochastic fluctuating sources using dynamic power conditioningSOURKOUNIS, C; RICHTER, F.International journal of energy technology and policy. 2007, Vol 5, Num 3, pp 271-279, issn 1472-8923, 9 p.Article

Direct contact PCM―water cold storageMARTIN, Viktoria; BO HE; SETTERWALL, Fredrik et al.Applied energy. 2010, Vol 87, Num 8, pp 2652-2659, issn 0306-2619, 8 p.Article

Effects of microcrystalline cellulose on suspension stability of cocoa beverageYAGINUMA, Yoshihito; KIJIMA, Tsuyoshi.Journal of dispersion science and technology. 2006, Vol 27, Num 7, pp 941-948, issn 0193-2691, 8 p.Article

Mémoires à semiconducteurs = Solid state memoriesBOREL, J.sd, pp 1-6Article

Beam-induced seeded lateral epitaxy with suppressed impurity diffusion for a three-dimensional DRAM cell fabricationOHKURA, M; KUSUKAWA, K; SUNAMI, H et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 2, pp 333-339, issn 0018-9383, 7 p.Article

A 2-υm CMOS 10-MHz microprogrammable signal processing core with an on-chip multiport memory bankWELTEN, F. P. J. M; DELARUELLE, A; VAN WYK, F. J et al.IEEE journal of solid-state circuits. 1985, Vol 20, Num 3, pp 754-760, issn 0018-9200Article

A novel JCMOS dynamic RAM cell for VLSI memoriesELDIN, A. G; ELMASRY, M. I.IEEE journal of solid-state circuits. 1985, Vol 20, Num 3, pp 715-723, issn 0018-9200Article

Charge storage and charge transfer in dynamic memoriesBECKER, J. D.Lecture notes in physics. 1983, Num 196, pp 53-68, issn 0075-8450Article

Circuit autotestable pour la correction d'erreur en mémoire dynamique = Autotestable circuit for the error correction in dynamic memoryGOBBI, J.-M; RAINARD, J.-L.1983, 38 p.Report

MEMOIRE DYNAMIQUEBERDICHEVSKIJ ZM; KAJKOV VN.1976; PRIBORY TEKH. EKSPER.; S.S.S.R.; DA. 1976; NO 3; PP. 80-81; BIBL. 1 REF.Article

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architectureINOUE, M; YAMADA, T; AOI, N et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1104-1112, issn 0018-9200Article

A 20-ns 128-kbit×4 high-speed DRAM with 330-Mbit/s data rateLU, N. C. C; CHAO, H. H; WEI HWANG et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1140-1149, issn 0018-9200Article

A 60-ns 16-Mbit CMOS DRAM with a transposed date-line structureAOKI, M; NAKAGOME, Y; ITOH, K et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1113-1119, issn 0018-9200Article

DYNAMISCHE HALBLEITERSPEICHER MIT DREITRANSISTORZELLE = MEMOIRE DYNAMIQUE A SEMICONDUCTEURS UTILISANT UNE CELLULE A TROIS TRANSISTORSJORKE G.1978; RADIO FERNSEHEN ELEKTRON.; DDR; DA. 1978; VOL. 27; NO 10; PP. 649-652; BIBL. 3 REF.Article

TESTING LARGE DYNAMIC MEMORIES.FLANINGAM D.1976; IN: INT. ELECTRON. PACKAG. PROD. CONF. PROC. TECH. PROGRAMME; BRIGHTON, ENGL.; 1976; SURBITON; KIVER COMMUNICATIONS; DA. 1976; PP. 181-186Conference Paper

Comment on the spreading dynamics of a liquid drop on a viscoelastic solidHILLS, D. A; SACKFIELD, A.Journal of physics. D, Applied physics (Print). 1989, Vol 22, Num 2, pp 371-372, issn 0022-3727, 2 p.Article

An optically delineated 4.2-μm2 self-aligned isolated-plate stacked-capacitor DRAM cellKIMURA, S.-I; KAWAMOTO, Y; HASEGAWA, N et al.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 10, pp 1591-1595, issn 0018-9383Article

The impact of data-line interference noise on DRAM scalingNAKAGOME, Y; AOKI, M; IKENAGA, S et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1120-1127, issn 0018-9200Article

Dynamic cross-coupled bit-line content addressable memory cell for high-density arraysWADE, J. P; SODINI, C. G.IEEE journal of solid-state circuits. 1987, Vol 22, Num 1, pp 119-121, issn 0018-9200Article

A lumped-state model of clustering in dynamic storage allocationREEVES, C. M.Computer journal (Print). 1984, Vol 27, Num 2, pp 135-142, issn 0010-4620Article

Moisture induced failures in plastic encapsulated 64 kbit dynamic RAMsSATOH, Y; IWAMORI, K; SAWADA, K et al.Japanese journal of applied physics. 1984, Vol 23, Num 5, pp L274-L276, issn 0021-4922, 2Article

THE 64 K DYNAMIC R.A.M.YOUNG S.1980; NEW ELECTRON.; GBR; DA. 1980; VOL. 13; NO 14; PP. 47-48Article

A 128 K word×8 bit dynamic RAMSUZUKI, S; NAKAO, M; TAKESHIMA, T et al.IEEE journal of solid-state circuits. 1984, Vol 19, Num 5, pp 624-627, issn 0018-9200Article

Shared word line DRAM cellSCHEUERLEIN, R. E; WALKER, W. W; MORENCY, D. G et al.IEEE journal of solid-state circuits. 1984, Vol 19, Num 5, pp 640-645, issn 0018-9200Article

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